1. Field of the Invention
This invention relates to a processor and, more particularly, to a processor shift and rotate circuit. This invention still more particularly relates to a shift and rotate circuit for a processor which divides each received word into a plurality of bytes and then performs logical and arithmetical operations on each word on a byte-by-byte basis.
2. Description of the Prior Art
Shift and rotate circuits are well known and are a necessary part of any data processor which must perform arithmetical and/or logical operations with a minimum of execution time. These circuits permit processors to perform the operations specified by various high-level programming languages. For example, if a specified field of a plural field word is to be tested, analyzed, or compared for the existence or nonexistence of a specified condition, shift and rotate circuits are used to move the specified field to the right so that it occupies the least significant portion of the word. This permits the processor gating and logic circuitry to test the contents of the shifted field to see if it meets the specified condition. Since logical operations of this type are extensively used, it is an economic necessity that processors be equipped with shift and rotate circuits that perform their required functions with a minimum of execution time.
The prior art discloses efficient shift and rotate circuits for use with processors which internally move, manipulate, and perform logical and arithmetic operations upon words of the same bit size as the words received from the I/O system with which the processor communicates. For example, U.S. Pat. No. 3,374,463 to D. Muir of Mar. 19, 1968 discloses a shift and rotate circuit which operates on a word while it is being transferred from one part of the processor to the other. Although these prior art shift and rotate circuits adequately perform their intended function, they are limited in their applicability to processors which internally operate upon words of the same bit size as those received from the I/O facilities. This is a problem since with the advent of large scale integration, it is known to use processors which receive 16-bit words from the I/O facilities, break each word down into a plurality of multibit bytes, and perform logical and arithmetical operations by manipulating the bytes one at a time in sequence. Most of the prior art shift and rotate circuits are unsuitable for use with byte-by-byte type processors.
Shift and rotate circuits are known for 4-bit byte processors such as, for example, the processor in the Nova series of computers manufactured by the Data General Corporation of Southboro, Mass. However, the shift and rotate circuits of these machines operate in such a manner that each byte can be shifted only one bit at a time. Thus, if an 8-bit shift of a 16-bit word is required, eight consecutive shift operations must be performed with each operation typically requiring three separate machine instructions. If a machine instruction has an approximate execution time of one microsecond, an 8-bit shift would require an execution time of eight times three or 24 microseconds. Thus, it can be seen that shift and rotate operations can require a significant amount of real time when performed on a bit-by-bit basis. This is disadvantageous since shift and rotate operations are extensively used and the expenditure of this amount of real time for such frequently performed operations limits the amount of work a machine can perform.